Exemplary embodiments relate generally to an integrated circuit, and more particularly to a semiconductor memory device and an erase method thereof.
A semiconductor memory device may be divided into a volatile memory device and a nonvolatile memory device. The volatile memory device requires power to retain the stored data, whereas the nonvolatile memory device retains data stored in the device even in absence of power.
With continued miniaturization of electronic devices, the efforts to highly integrate the semiconductor devices continue.
Also, data storage capacity of a memory device can be increased by configuring each memory cell to store more than one bit. This type of a memory cell is called a multi-level cell (MLC), whereas a memory cell for storing a single bit is called a single level cell (SLC).
In general, the semiconductor memory device includes memory blocks each including a plurality of memory cells, and, according to a known art, an erase operation is performed by the memory block.
In other words, although the semiconductor memory device can be read or programmed a page at a time, it can only be erased a “block” at a time.
Memory cells can be programmed by storing charges in a charge storage site. For example, NAND Flash memory device can be programmed by Fowler-Nordheim (F-N) tunneling. When high voltage is supplied to the control gates of memory cells in the program operation, electrons are accumulated in the floating gates. In the read operation, the threshold voltages of the memory cells, varied according to the amount of electrons accumulated in the floating gates, are detected, and stored data is determined according to the detected threshold voltages.
However, the memory cells may be degraded due to a large number of erase/write (E/W) cycles, and the threshold voltages of the memory cells of an erase state rise when electrons remain in the floating gates even after the erase operation.
Therefore, various methods such as changing a program voltage or a data read voltage according to the number of the erase/write (E/W) cycles are being developed.